Field of the Invention
The present invention generally relates to memory systems and more specifically to a compression status bit cache and backing store.
Description of the Related Art
Performance requirements are constantly increasing in data processing systems, which conventionally comprise one or more processor chips and attached memory devices. The processor chip includes on-chip data processing resources and memory interface circuitry configured to enable the processing resources to access off-chip, attached memory. System performance is generally determined by the on-chip data processing performance and available bandwidth to the attached memory devices.
One technique for increasing available memory bandwidth is to interleave memory access over two or more memory partitions. When multiple on-chip clients access memory within each partition, the associated access requests may be scheduled to optimize specific parameters, such as overall system throughput or average latency for a specific client. Clients of the memory system, such as on-chip data processing resources, may post memory access requests through a switched network to one or more memory partitions. A physical address associated with a memory access request is converted to a local partition addresses using an address mapping function that is specific to a given partition configuration.
To further improve memory bandwidth, some data may be stored in a compressed format, which reduces the number of bits needed to represent a block of original data. The amount of memory allocated to store a block of original data in a compressed format is not reduced compared to an uncompressed format, but the number of bits needed to store and retrieve the compressed block of data is reduced and therefore memory bandwidth is reduced. A plurality of both loss-less and lossy compressed formats may be used, depending on specific application requirements and whether a specific block of original data is compressible under available compression algorithms. Each compression format advantageously reduces the number of bits needed to represent a block of original data stored in attached memory. However, the specific number of bits and how to interpret the bits is a function of which compression format, if any, is used to represent the block of original data. A selected compression format associated with each block is indicated by compression status bits for each block of compressible memory. In order to minimize bandwidth needed to access a given block of data within attached memory, the memory interface circuitry residing on the processor chip needs to refer to the compression status bits associated with the block of memory prior to initiating a memory access request to the attached memory.
To maximize performance, the compression status bits need to be available to the memory interface circuitry. One solution involves storing compression status bits in an on-chip random access memory (RAM), referred to herein as the compression status RAM, wherein the status bits map directly to blocks of memory within a region of compressible memory residing in the attached memory. In this solution, a given set of compression status bits within the compression status RAM indicates compression status for a directly corresponding block of physical memory within the attached memory. When the memory interface circuitry within a partition receives a memory access request, the memory interface circuitry queries the compression status RAM prior to initiating a memory access request to the attached memory.
As data processing systems increase in performance and expand overall capabilities, total attached memory is also conventionally increased. Because the on-chip compression status RAM directly map to compressible attached memory, increasing the amount of attached memory implies an increase in the size of the compression status RAM. For example, doubling the amount of attached memory should result in doubling the size of the compression status RAM to accommodate the additional blocks of potentially compressed memory. However, on-chip storage of compression status bits is relatively expensive in terms of die area and, unlike attached memory, can not be easily doubled.
Accordingly, what is needed in the art is a technique that enables a data processing system to support large amounts of attached storage without incurring die area costs that are associated with storing large numbers of directly mapped on-chip compression status bits.